1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to techniques for reducing chip-package interactions caused by thermal mismatch between the chip and the package, in particular during reflowing a bump structure for directly connecting the chip and the package.
2. Description of the Related Art
Semiconductor devices are typically formed on substantially disc-shaped substrates made of any appropriate material. The majority of semiconductor devices including highly complex electronic circuits are currently, and in the foreseeable future will be, manufactured on the basis of silicon, thereby rendering silicon substrates and silicon-containing substrates, such as silicon-on-insulator (SOI) substrates, viable base materials for forming semiconductor devices, such as microprocessors, SRAMs, ASICs (application specific ICs), systems on chip (SoC) and the like. The individual integrated circuits are arranged in an array on the wafer, wherein most of the manufacturing steps, which may involve several hundred and more individual process steps in sophisticated integrated circuits, are performed simultaneously for all chip areas on the substrate, except for photolithography processes, metrology processes and packaging of the individual devices after dicing the substrate. Thus, economic constraints drive semiconductor manufacturers to steadily increase the substrate dimensions, thereby also increasing the area available for producing actual semiconductor devices and thus increasing production yield. Additionally, the size of the individual die regions on the wafer is increased in order to integrate more and more circuit portions, even of very different type, thereby achieving very complex integrated circuits executing sophisticated tasks.
In addition to increasing the substrate area, it is also important to optimize the utilization of the substrate area for a given substrate size so as to actually use as much substrate area as possible for semiconductor devices and/or test structures that may be used for process control. In an attempt to maximize the useful surface area for a given substrate size, the feature sizes of circuit elements are steadily scaled down. Due to this ongoing demand for shrinking the feature sizes of highly sophisticated semiconductor devices, copper, in combination with a low-K dielectric material, has become a frequently used alternative in the formation of so-called interconnect structures comprising metal line layers and intermediate via layers that include metal lines as intra-layer connections and vias as inter-layer or vertical connections, which commonly connect individual circuit elements to provide the required functionality of the integrated circuit. Typically, a plurality of metal line layers and via layers stacked on top of each other are necessary to realize the connections between all internal circuit elements and I/O (input/output), power and ground pads of the circuit design under consideration.
For extremely scaled integrated circuits, the signal propagation delay is no longer limited by the circuit elements, such as field effect transistors and the like, but is limited, owing to the increased density of circuit elements requiring an even more increased number of electrical connections, by the close proximity of the metal lines, since the line-to-line capacitance is increased, while the conductivity of the lines is reduced due to a reduced cross-sectional area. For this reason, traditional dielectrics, such as silicon dioxide (k>3.6) and silicon nitride (k>5), are replaced by dielectric materials having a lower permittivity, which are, therefore, also referred to as low-k dielectrics having a relative permittivity of 3 or less. However, the density and mechanical stability or strength of the low-k materials may be significantly less compared to the well-approved dielectrics silicon dioxide and silicon nitride. As a consequence, during the formation of the metallization system and any subsequent manufacturing processes of integrated circuits, production yield may depend on the mechanical characteristics of sensitive dielectric materials, such as low-k dielectric layers, and their adhesion to other materials.
Due to the reduced mechanical stability of advanced dielectric materials having a dielectric constant of 3.0 and less, device reliability may be affected by the provision of these materials during operation of sophisticated semiconductor devices and in particular during the further processing of the device caused by the interaction between a chip and the package due to a thermal mismatch of the corresponding thermal expansion of the different materials. For instance, in the fabrication of complex integrated circuits, increasingly, a contact technology may be used in connecting the package carrier to the chip, which is known as flip chip packaging technique. Contrary to the well-established wire bonding techniques in which appropriate contact pads may be positioned at the periphery of the very last metal layer of the chip, which may be connected to corresponding terminals of the package by a bond wire, in the flip chip technology, a respective bump structure may be formed on the last metallization layer, for instance comprised of a solder material which may be brought into contact with respective contact pads of the package. Thus, after reflowing the bump material, a reliable electrical and mechanical connection may be established between the last metallization layer and the contact pads of the package carrier. In this manner, a very large number of electrical connections may be provided across the entire chip area of the last metallization layer with reduced contact resistance and parasitic capacitance, thereby providing the IO (input/output) capabilities, which may be required for complex integrated circuits, such as CPUs, storage devices and the like. During the corresponding process sequence for connecting the bump structure with a package carrier, a certain degree of pressure and/or heat may be applied to the composite device so as to reflow the solder material and establish a reliable connection between each of the bumps formed on the chip and the bumps or pads that may be provided on the package substrate. The thermally or mechanically induced stress may, however, also act on the lower lying metallization layers, which may typically include low-k dielectrics.
Consequently, in sophisticated semiconductor devices, the mechanical characteristics of the low-k dielectric materials have been appropriately adjusted in order to provide the required degree of mechanical stability during the further processing and during the operation of the packaged semiconductor device. Since overall performance of sophisticated semiconductor devices is substantially determined by the signal propagation delay caused by the complex metallization system, great efforts have been made in order to further reduce the parasitic capacitance in the metallization system by further reducing the dielectric constant of the dielectric materials used therein. To this end, so-called ULK (ultra low-k) dielectric materials have been developed, which may typically represent dielectric materials with a porous structure, which may be formed on the basis of lithography techniques or on the basis of process techniques and materials, in which a nano-porous structure may be induced. For example, appropriate species may be incorporated into a base material which may already have a reduced dielectric constant and, upon a subsequent treatment, for instance in the form of a heat treatment, a radiation treatment and the like, a significant portion of the species may be driven out of the base material, thereby producing a random network of pores within the base material, which may thus represent a plurality of randomly distributed “air gaps” in the base material, thereby further reducing the overall dielectric constant. In this manner, the dielectric constant may be reduced to values of 2.7 and less, which may translate into superior electrical performance of the metallization system. In this respect, it should be appreciated that the dielectric constant of dielectric materials may be estimated on the basis of well-established measurement techniques, for instance by forming an appropriate capacitive structure on any test substrates or test regions and measuring the electrical response of the capacitive structure to an electrical stimulus. From the corresponding electrical response, the dielectric constant of the dielectric material may be readily determined. Similarly, a dielectric constant value may be associated with a certain dielectric material by determining its material composition, including the degree of porosity, and measuring the dielectric constant for any appropriate capacitive structure using the material composition of interest. It should be noted that any values for a dielectric constant may thus be understood as referring to a certain measurement strategy, wherein, typically, the corresponding measurement results for the dielectric constant may vary by less than 2-5 percent. In this sense, a value for the dielectric constant of 2.7 may thus enclose a variation within the above-specified range due to a difference in measurement strategies.
The introduction of ULK dielectric materials or porous dielectric materials into the metallization system of sophisticated semiconductor devices, however, may be associated with a further reduction of the mechanical stability of the complex metallization systems, which may thus require a precise balance between electrical performance and mechanical strength of the metallization system. In most recent developments, the continuous shrinkage of critical dimensions for the individual semiconductor-based circuit elements, such as field effect transistors and the like, has brought about an even further increased packing density, thereby providing the possibility to integrate more and more functions into a single semiconductor die. Furthermore, due to advances in process tool technology and the like, and due to the demand for providing semiconductor chips having incorporated therein more and more functional circuit portions, the die size has been increased, thereby requiring very complex metallization systems in which a significant portion of the dielectric material may be provided in the form of ULK or porous dielectric materials. Although the mechanical characteristics and the electrical performance may be the subject of thorough investigations and many process control strategies have been developed to ensure the required reliability of the metallization system, recently, increased yield losses have been observed in combination with advanced direct contact regimes, which may have to be performed on the basis of lead-free solder materials.
With reference to FIGS. 1a-1b, a complex conventional semiconductor device packaged on the basis of a lead-free contact regime will now be described in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a packaged state. That is, the semiconductor device 100 comprises a semiconductor die 150 comprising a substrate 151 and a plurality of device levels formed above the substrate 151. As previously explained, the substrate 151 typically represents a silicon material or any other appropriate carrier material for forming thereon semiconductor-based circuit elements, such as transistors and the like. For convenience, any such circuit elements are not shown in FIG. 1a. Furthermore, a metallization system 160 is formed above the substrate 151 and typically comprises a plurality of metal line layers, such as layers 120 and 130, with intermediate via layers, wherein, for convenience, a single via layer 140 is illustrated in FIG. 1a. Furthermore, a contact structure or bump structure 110 is provided above the substrate 151 and may be considered as a part of the metallization system 160. The bump structure 110 comprises an appropriate dielectric material 111 and a bump system 112 comprising a plurality of contact elements or bumps 112A which, as previously indicated, are formed of a lead-free material system. For example, the bump system 112 may be comprised of copper, aluminum, tin, gold, silver and the like, or any appropriate composition of lead-free materials.
Furthermore, the packaged semiconductor device 100 comprises a carrier substrate or package substrate 170, which may have any appropriate configuration and which comprises a complementary contact or bump structure 175 including appropriate contact elements or contact pads 175A that may be directly connected to the respective bump or contact elements 112A of the contact structure 110.
Generally, the packaged semiconductor device 100 may be formed on the basis of appropriate manufacturing strategies for providing circuit elements and the metallization system 160 in accordance with device requirements. In particular, the metallization system 160 is typically provided in the form of sophisticated materials comprising ultra low-k dielectrics, as will be described in more detail with reference to FIG. 1b. Furthermore, as discussed above, with the demand for the integration of more and more functions into the semiconductor die 150, appropriately selected lateral dimensions of the die 150 have to be provided, thereby, however, increasing the probability of creating serious damage, in particular in the metallization system 160, upon connecting the die 150 and the package substrate 170. During a corresponding process, the package substrate 170 and the semiconductor die 150 are mechanically contacted and are heated so as to reflow any solder material, for instance provided in the form of the bumps 112A and/or in the form of the contact elements 175A, so as to form, after solidification of the reflowed solder material, an intermetallic connection between the contact structure 110 and the contact structure 175. Upon using a lead-free contact regime, typically, increased reflow temperatures are required due to the higher melting point of the corresponding lead-free solder materials. Consequently, generally, any temperature gradients, which may be induced during the reflow process, may also be increased. Additionally, the lead-free materials in the contact structures 175, 110 may have an increased degree of stiffness compared to lead-containing solder materials so that any mechanical shear forces created during the reflow process may not be efficiently compensated for or buffered by the lead-free materials in the contact structures 175, 110. Typically, the package substrate 170 may have a significantly greater coefficient of thermal expansion compared to the semiconductor die 150, which may result in a significant deformation of the composite device 100 during the reflow process, in particular during the solidification, when preferably the peripheral contact elements cool down faster compared to the central contact elements. Consequently, the increased overall area of the semiconductor die 150 in combination with increased stiffness of the lead-free contact structures 175, 110 may thus result in increased mechanical stress forces in the metallization system 160. Since a significant part of the metallization system 160 may be comprised of sophisticated ULK materials, such as the material 131 in the metal line layer 130 and the via layer 140, significant shear forces may be transferred into these sensitive material systems. On the other hand, non-porous or mechanically robust dielectric materials, such as layers 141, 142, may preferably be provided in the via layer 140 in combination with the low-k dielectric material 131 so as to obtain increased mechanical stability and also provide chemical resistivity and the like. It should be noted that, according to well-established technical expertise, the via layer 140 may comprise a significant amount of the ultra low-k dielectric material 131 in order to obtain a desired balance between mechanical integrity and overall signal process performance.
FIG. 1b schematically illustrates a portion of the metallization system 160 of the semiconductor die 150 in a more detailed illustration. As shown, a first metal line layer 120 may comprise any appropriate dielectric material 121, such as a porous ULK material, in which metal lines 125 are formed. Moreover, the metal line layer 130 is formed above the metal line layer 120 and is electrically connected thereto by means of the intermediate via layer 140. The layer 130 comprises the ULK material 131 having a porous configuration and includes appropriate metal lines 135, which may be comprised of a conductive barrier material or material system 135A in combination with a core metal 135B. Typically, tantalum and tantalum nitride may be used as efficient barrier materials and the core metal may be provided in the form of copper and the like. As illustrated, the barrier material 135A and the core metal 135B may continuously connect and thus form a via 145 that is thus laterally embedded in the dielectric materials 131, 141 and 142 of the via layer 140.
The metallization system 160 is formed on the basis of the following processes. After completing the metal line layer 120, the dielectric material 142 is deposited, for instance in the form of a nitrogen-containing silicon carbide material and the like, which may provide superior etch stop capabilities and may also act as an efficient copper diffusion blocking layer, if required. However, due to the incorporation of nitrogen, the layer 142 may have a moderately high dielectric constant of approximately 4.5 and higher. Thereafter, a further dielectric material 141, for instance in the form of silicon dioxide formed on the basis of TEOS, may be provided with a dielectric constant of 3.5 and higher, depending on the actual material composition. Thereafter, a dielectric material may be deposited and may be appropriately treated in order to obtain the desired porous state, which may be accomplished on the basis of a plurality of low-k base materials in combination with any substances that may be incorporated into the base material. Consequently, after treating the base material, the low-k dielectric material 131 in the via layer 140 and the metal line layer 130 may be obtained. Thereafter, a complex patterning process is typically performed comprising two lithography processes in order to form etch masks for defining the lateral size and position of the vias 145 and of the metal lines 135. Thereafter, the materials 135A and 135B may be provided on the basis of any appropriate process strategy, followed by the removal of any excess material. In this manner, any further metal lines and intermediate via layers may be provided, wherein at least some of these further layers may have incorporated therein an ultra low-k dielectric material.
In particular, after the reflow process as described with reference to FIG. 1a, significant damage may be observed in the metallization system 160, such as cracks and material delamination, which may result in significant device failures and thus yield losses. It is believed that the large amount of ULK material may significantly reduce the overall mechanical stability while, according to standard technological expertise, a reduction of the amount of ULK material in the metallization system 160 may result in significant loss of performance of the semiconductor die 150.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.